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1

Methods for joint optimization of mask and design targets for improving lithographic process window

Banerjee, Shayak, Agarwal, Kanak B., Orshansky, Michael

Journal:

Journal of Micro/Nanolithography MEMS and MOEMS

Year:

2013

Language:

english

File:

PDF, 5.05 MB

english, 2013

2

How poverty is measured

MOLLIE ORSHANSKY

Journal:

Monthly Labor Review

Year:

1969

Language:

english

File:

PDF, 830 KB

english, 1969

3

[IEEE IEEE 2000 Custom Integrated Circuits Conference - Orlando, FL, USA (21-24 May 2000)] Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) - New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Cao, Y., Sato, T., Orshansky, M., Sylvester, D., Hu, C.

Year:

2000

Language:

english

File:

PDF, 463 KB

english, 2000

4

An accurate sparse-matrix based framework for statistical static timing analysis

Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan

Journal:

Integration, the VLSI Journal

Year:

2012

Language:

english

File:

PDF, 427 KB

english, 2012

5

[IEEE 2012 IEEE International Reliability Physics Symposium (IRPS) - Anaheim, CA, USA (2012.04.15-2012.04.19)] 2012 IEEE International Reliability Physics Symposium (IRPS) - Abnormal ESD failure mode with low-voltage turn-on phenomenon of LDMOS output driver

Park, Jaeyoung, Orshansky, Michael

Year:

2012

Language:

english

File:

PDF, 489 KB

english, 2012

6

[IEEE 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) - Washington, DC, USA (2018.4.30-2018.5.4)] 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) - Fresh re-keying with strong PUFs: A new approach to side-channel security

Xi, Xiaodan, Aysu, Aydin, Orshansky, Michael

Year:

2018

Language:

english

File:

PDF, 576 KB

english, 2018

7

Velocity overshoot of electrons and holes in Si inversion layers

D Sinitsky, F Assaderaghi, M Orshansky, J Bokor, C Hu

Journal:

Solid-State Electronics

Year:

1997

Language:

english

File:

PDF, 583 KB

english, 1997

8

Effect of suspended solids on wastewater disinfection efficiency by chlorine dioxide

Nava Narkis, Robert Armon, Regina Offer, Frieda Orshansky, Eugenia Friedland

Journal:

Year:

1995

Language:

english

File:

PDF, 601 KB

english, 1995

9

[IEEE 2013 18th IEEE European Test Symposium (ETS) - Avignon, France (2013.05.27-2013.05.30)] 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS) - Approximate computing: An emerging paradigm for energy-efficient design

Han, Jie, Orshansky, Michael

Year:

2013

Language:

english

File:

PDF, 1.66 MB

english, 2013

10

Shape slack: a design-manufacturing co-optimization methodology using tolerance information

Banerjee, Shayak, Agarwal, Kanak B., Nassif, Sani, Orshansky, Michael

Journal:

Journal of Micro/Nanolithography MEMS and MOEMS

Year:

2013

Language:

english

File:

PDF, 2.25 MB

english, 2013

11

[IEEE 2010 IEEE Custom Integrated Circuits Conference -CICC 2010 - San Jose, CA, USA (2010.09.19-2010.09.22)] IEEE Custom Integrated Circuits Conference 2010 - Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects

Banerjee, Shayak, Agarwal, Kanak, Orshansky, Michael

Year:

2010

Language:

english

File:

PDF, 252 KB

english, 2010

12

[ACM Press the 35th annual conference - San Francisco, California, United States (1998.06.15-1998.06.19)] Proceedings of the 35th annual conference on Design automation conference - DAC '98 - A statistical performance simulation methodology for VLSI circuits

Orshansky, Michael, Chen, James C., Hu, Chenming

Year:

1998

Language:

english

File:

PDF, 288 KB

english, 1998

13

[ACM Press the The 51st Annual Design Automation Conference - San Francisco, CA, USA (2014.06.01-2014.06.05)] Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14 - Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization

Wang, Ye, Orshansky, Michael, Caramanis, Constantine

Year:

2014

Language:

english

File:

PDF, 320 KB

english, 2014

14

[IEEE 2017 Symposium on VLSI Circuits - Kyoto, Japan (2017.6.5-2017.6.8)] 2017 Symposium on VLSI Circuits - A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell

Jeloka, Supreet, Yang, Kaiyuan, Orshansky, Michael, Sylvester, Dennis, Blaauw, David

Year:

2017

Language:

english

File:

PDF, 413 KB

english, 2017

15

Disinfection of effluents by combinations of chlorine dioxide and chlorine

N. Narkis, A. Katz, F. Orshansky, Y. Kott, Y. Friedland

Journal:

Water Science and Technology

Year:

1995

Language:

english

File:

PDF, 807 KB

english, 1995

16

Spice up your MOSFET modelling

Yu Cao, Orshansky, M., Sato, T., Sylvester, D., Chenming Hu

Journal:

IEEE Circuits and Devices Magazine

Year:

2003

Language:

english

File:

PDF, 13.17 MB

english, 2003

17

Disinfection of effluent by combinations of equal doses of chlorine dioxide and chlorine added simultaneously over varying contact times

Anat Katz, Nava Narkis, Frieda Orshansky, Evgenia Friedland, Yehuda Kott

Journal:

Year:

1994

Language:

english

File:

PDF, 551 KB

english, 1994

18

Characteristics of organics removal by PACT simultaneous adsorption and biodegradation

Frieda Orshansky, Nava Narkis

Journal:

Year:

1997

Language:

english

File:

PDF, 680 KB

english, 1997

19

Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation

Wei-Shen Wang, Michael Orshansky

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2006

Language:

english

File:

PDF, 315 KB

english, 2006

20

A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits

Mani, M., Devgan, A., Orshansky, M., Yaping Zhan

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2007

Language:

english

File:

PDF, 593 KB

english, 2007

21

Exploring Barriers and Facilitators to the Use of Computerized Clinical Reminders

Jason J. Saleem, Emily S. Patterson, Laura Militello, Marta L. Render, Greg Orshansky, Steven M. Asch

Journal:

Journal of the American Medical Informatics Association

Year:

2005

Language:

english

File:

PDF, 394 KB

english, 2005

22

Sol-gel applications in environmental biotechnology

R. Armon, C. Dosoretz, J. Starosvetsky, F. Orshansky, I. Saadi

Journal:

Journal of Biotechnology

Year:

1996

Language:

english

File:

PDF, 528 KB

english, 1996

23

Efficient generation of pre-silicon MOS model parameters for early circuit design

Orshansky, M., An, J., Chun Jiang, Liu, B., Riccobene, C., Chenming Hu

Journal:

IEEE Journal of Solid-State Circuits

Year:

2001

Language:

english

File:

PDF, 103 KB

english, 2001

24

Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits

Orshansky, M., Milor, L., Pinhong Chen, Keutzer, K., Chenming Hu

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2002

Language:

english

File:

PDF, 406 KB

english, 2002

25

The Search for Alternative Computational Paradigms

Shanbhag, N.R., Mitra, S., de Veciana, G., Orshansky, M., Marculescu, R., Roychowdhury, J., Jones, D., Rabaey, J.M.

Journal:

IEEE Design & Test of Computers

Year:

2008

Language:

english

File:

PDF, 618 KB

english, 2008

26

ACTIN-BINDING PROTEINS: HOW TO REVEAL THE CONFORMATIONAL CHANGES

SINITSINA, NATALIA, ORSHANSKY, IGOR, SOKOLOVA, OLGA

Journal:

Journal of Bioinformatics and Computational Biology

Year:

2008

Language:

english

File:

PDF, 504 KB

english, 2008

27

Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics

Singh, Ashish Kumar, Ragab, Kareem, Lok, Mario, Caramanis, Constantine, Orshansky, Michael

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2012

Language:

english

File:

PDF, 3.36 MB

english, 2012

28

Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems

He, Ku, Gerstlauer, Andreas, Orshansky, Michael

Journal:

IEEE Transactions on Circuits and Systems for Video Technology

Year:

2013

Language:

english

File:

PDF, 7.74 MB

english, 2013

29

[IEEE 2006 IEEE/ACM International Conference on Computer Aided Design - Double Tree Hotel, San Jose, CA,USA (2006.11.5-2006.11.9)] 2006 IEEE/ACM International Conference on Computer Aided Design - Analytical Modeling of SRAM Dynamic Stability

Zhang, Bin, Arapostathis, Ari, Nassif, Sani, Orshansky, Michael

Year:

2006

Language:

english

File:

PDF, 8.96 MB

english, 2006

30

Probabilistic strain optimization under constraint uncertainty

Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun

Journal:

BMC Systems Biology

Year:

2013

Language:

english

File:

PDF, 288 KB

english, 2013

31

[IEEE Proceedings of 39th Design Automation Conference - New Orleans, LA, USA (2002.6.10-2002.6.14)] Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) - A general probabilistic framework for worst case timing analysis

Orshansky, M., Keutzer, K.

Year:

2002

Language:

english

File:

PDF, 684 KB

english, 2002

32

[IEEE 2006 IEEE/ACM International Conference on Computer Aided Design - Double Tree Hotel, San Jose, CA,USA (2006.11.5-2006.11.9)] 2006 IEEE/ACM International Conference on Computer Aided Design - An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

Ramalingam, Anand, Nam, Gi-joon, Singh, Ashish, Orshansky, Michael, Nassif, Sani, Pan, David

Year:

2006

Language:

english

File:

PDF, 6.86 MB

english, 2006

33

[IEEE 2013 14th International Symposium on Quality Electronic Design (ISQED 2013) - Santa Clara, CA (2013.3.4-2013.3.6)] International Symposium on Quality Electronic Design (ISQED) - Low-energy digital filter design based on controlled timing error acceptance

Ku He,, Gerstlauer, A., Orshansky, M.

Year:

2013

Language:

english

File:

PDF, 715 KB

english, 2013

34

[IEEE 2006 Design Automation Conference - San Francisco, CA, USA ()] 2006 43rd ACM/IEEE Design Automation Conference - Gain-based technology mapping for minimum runtime leakage under input vector uncertainty

Singh, A.K., Mani, M., Puri, R., Orshansky, M.

Year:

2006

Language:

english

File:

PDF, 3.25 MB

english, 2006

35

[IEEE 2010 IEEE Dallas Circuits and Systems Workshop (DCAS) - Richardson, TX, USA (2010.10.17-2010.10.18)] 2010 IEEE Dallas Circuits and Systems Workshop - Design of power-optimal buffers tunable to process variability

Lok, Mario, He, Ku, Mani, Murari, Caramanis, Constantine, Orshansky, Michael

Year:

2010

File:

PDF, 255 KB

2010

36

[IEEE 2007 IEEE International Symposium on Nanoscale Architectures - San Jose, CA, USA (2007.10.21-2007.10.22)] 2007 IEEE International Symposium on Nanoscale Architectures - A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions

Ashish Singh,, Hady Ali Zeineddine,, Adnan Aziz,, Sriram Vishwanath,, Orshansky, Michael

Year:

2007

Language:

english

File:

PDF, 202 KB

english, 2007

37

[IEEE 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) - San Jose, CA, USA (2008.11.10-2008.11.13)] 2008 IEEE/ACM International Conference on Computer-Aided Design - Electrically driven optical proximity correction based on linear programming

Banerjee, Shayak, Elakkumanan, Praveen, Liebmann, Lars W., Orshansky, Michael

Year:

2008

Language:

english

File:

PDF, 478 KB

english, 2008

38

[IEEE 7th International Symposium on Quality Electronic Design (ISQED'06) - San Jose, CA, USA (27-29 March 2006)] 7th International Symposium on Quality Electronic Design (ISQED'06) - Tutorial II: Variability and Its Impact on Design

Bowman, K., Orshansky, M., Sapatnekar, S.S.

Year:

2006

Language:

english

File:

PDF, 472 KB

english, 2006

39

[IEEE 2006 Design Automation Conference - San Francisco, CA, USA ()] 2006 43rd ACM/IEEE Design Automation Conference - Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty

Wei-Shen Wang,, Kreinovich, V., Orshansky, M.

Year:

2006

Language:

english

File:

PDF, 1.34 MB

english, 2006

40

[IEEE 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC - San Francisco, CA, USA (5-7 Feb. 1998)] 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156) - Statistical circuit characterization for deep-submicron CMOS designs

Chen, J., Orshansky, M., Chenming Hu,, Wan, C.-P.

Year:

1998

Language:

english

File:

PDF, 567 KB

english, 1998

41

[IEEE 2012 13th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2012.03.19-2012.03.21)] Thirteenth International Symposium on Quality Electronic Design (ISQED) - Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation

Ragab, Kareem, Gharpurey, Ranjit, Orshansky, Michael

Year:

2012

Language:

english

File:

PDF, 386 KB

english, 2012

42

[IEEE 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) - Austin, TX, USA (2013.06.2-2013.06.3)] 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) - Novel strong PUF based on nonlinearity of MOSFET subthreshold operation

Kalyanaraman, Mukund, Orshansky, Michael

Year:

2013

Language:

english

File:

PDF, 1.16 MB

english, 2013

43

[ACM ISLPED International Symposium on Low-Power Electronics and Design - Seoul, South Korea (25-27 Aug. 2003)] Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. - Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design]

Nguyen, D., Davare, A., Orshansky, M., Chinnery, D., Thompson, B., Keutzer, K.

Year:

2003

Language:

english

File:

PDF, 607 KB

english, 2003

44

Direct sampling methodology for statistical analysis of scaled CMOS technologies

Orshansky, M., Chen, J.C., Chenming Hu,

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

1999

Language:

english

File:

PDF, 113 KB

english, 1999

45

Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning

Singh, Ashish K., He, Ku, Caramanis, Constantine, Orshansky, Michael

Journal:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year:

2014

Language:

english

File:

PDF, 1.37 MB

english, 2014

46

[IEEE 2006 IEEE International Conference on IC Design and Technology - Padova, Italy ()] 2006 IEEE International Conference on IC Design and Technology - Statistical Minimization of Total Power under Timing Yield Constraints

Year:

2006

Language:

english

File:

PDF, 424 KB

english, 2006

47

Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction

Orshansky, M., Milor, L., Hu, C.

Journal:

IEEE Transactions on Semiconductor Manufacturing

Year:

2004

Language:

english

File:

PDF, 543 KB

english, 2004

48

[IEEE 7th International Symposium on Quality Electronic Design (ISQED'06) - San Jose, CA, USA (27-29 March 2006)] 7th International Symposium on Quality Electronic Design (ISQED'06) - FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs

Bin Zhang,, Wei-Shen Wang,, Orshansky, M.

Year:

2006

Language:

english

File:

PDF, 800 KB

english, 2006

49

[IEEE Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan (June 3-5, 1997)] Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications - An Extension Of BSIM3 Model Incorporating Velocity Overshoot

Sinitshy, D., Assaderaghi, F., Orshansky, M., Bokor, J., Chenming Hu,

Year:

1997

Language:

english

File:

PDF, 298 KB

english, 1997

50

[IEEE 2006 IEEE/ACM International Conference on Computer Aided Design - Double Tree Hotel, San Jose, CA,USA (2006.11.5-2006.11.9)] 2006 IEEE/ACM International Conference on Computer Aided Design - Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization

Mani, Murari, Singh, Ashish, Orshansky, Michael

Year:

2006

Language:

english

File:

PDF, 9.18 MB

english, 2006